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Digital Nanoelectronic Design

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Name

Digital Nanoelectronic Design

Summary

This is a Master’s course with the aim of designing digital medium-complexity CMOS integrated circuits, from hardware description to tapeout. In this course, specific attention will be given to low-power design techniques (dynamic power reduction; clock gating; static power reduction. power gating; dynamic voltage scaling) as well as practical aspects of VLSI design (interconnects; crosstalk; robustness and variability; power supply distribution; clock distribution; buffering; input/output pads; layout and tapeout; packaging). An introduction to test and verification will also be provided.